Product Briefs
Xillybus IP Core Product Brief
Xillyp2p IP Core Product Brief
A short overview and technical summary of the Xillybus IP core.
A short overview and technical summary of the Xillyp2p IP core.
Getting Started with Xillybus / XillyUSB
For information on Xillyp2p, refer to Xillyp2p's main page.
Getting started with the FPGA demo bundle for AMD
(pdf
|
web)
Getting started with the FPGA demo bundle for Altera
(pdf
|
web)
Getting started with Xillinux for Zynq-7000 EPP
(pdf
|
web)
Getting started with Xillinux for Cyclone V SoC (SoCKit)
(pdf
|
web)
Getting started with Xillybus on a Linux host
(pdf
|
web)
Getting started with Xillybus on a Windows host
(pdf
|
web)
A step-by-step guide, intended for novices as well as experienced FPGA engineers. Describes how to prepare the FPGA for running the Xillybus demo bundle on a PCIe-based board.
A step-by-step guide, intended for novices as well as experienced FPGA engineers. Describes how to prepare the FPGA for running the Xillybus demo bundle on a PCIe-based board.
A step-by-step guide, intended for novices as well as experienced FPGA engineers. Describes how to set up the Xillinux distribution for running the Zedboard as a graphical X-Windows computer.
A step-by-step guide, intended for novices as well as experienced FPGA engineers. Describes how to set up the Xillinux distribution for running the SoCKit board as a graphical X-Windows computer.
Installing the Xillybus driver for Linux (on distributions that don't have it pre-installed), running a simple command-line test, compiling and running sample host applications.
Installing the Xillybus driver for Microsoft Windows, running a simple command-line test, compiling and running sample host applications.
FPGA-related guides
Xillybus FPGA designer’s guide
(pdf
|
web)
The guide to Xillybus Lite
(pdf
|
web)
The guide to defining a custom Xillybus IP core
(pdf
|
web)
Intended for FPGA engineers: General guidelines for interfacing with the Xillybus IP core, signal description and application notes for implementing data acquisition and simulation.
The "xillycapture" code example can be downloaded here.
Describes the inclusion and usage of Xillybus Lite in a project targeting Zynq-7000. Covers logic design aspects as well as host programming considerations.
Note that this document doesn't cover Xillyp2p, which has separate documentation on the IP Core Factory.
Potential licensees are encouraged to request a tailored version of the Xillybus IP core for evaluation through the IP Core Factory. Even though the web interface's help boxes should cover the relevant subjects enough for defining a custom IP core, this document supplies some additional information.
Host programming guides
Xillybus host application programming guide for Linux
(pdf
|
web)
Xillybus host application programming guide for Windows
(pdf
|
web)
This guide is intended for host application programmers targeting Linux machines. It includes an explanation about synchronous vs. asynchronous streams, suggestions regarding I/O programming, and several application notes regarding high-rate data acquisition, frame buffering, packet communication, control, synchronization of data and more. This guide also walks through the RAM FIFO demo application available for download.
This guide is intended for host application programmers targeting Microsoft Windows machines. It includes an explanation about synchronous vs. asynchronous streams, suggestions regarding I/O programming, and several application notes regarding high-rate data acquisition, frame buffering, packet communication, control, synchronization of data, hibernation and more. This guide also walks through the RAM FIFO demo application available for download.
Tutorials
Several howto-style tutorials can be found on the tutorials main page.Unmaintained documentation
- A tutorial for working with Vivado's block design GUI instead of Verilog / VHDL coding, possibly with Vivado High Level Synthesis (HLS).
This method is no longer supported; however, the documentation is available in order to support existing designs:
The guide to Xillybus Block Design Flow for non-HDL users (pdf | web)