1 Introduction
2 General guidelines
2.1 Getting started
2.2 Notable elements in the block design
3 Integrating with application logic
3.1 The basics
3.2 Clocking
3.2.1 General
3.2.2 Setting the application clock
3.2.3 The bus_clk signal
4 Acceleration / coprocessing best practices
4.1 Throughput vs. latency
4.2 Data width and performance
4.3 Do’s and don’ts
5 Applying a custom Xillybus IP core
6 Vivado HLS integration
6.1 Overview
6.2 HLS synthesis
6.3 Integration with the FPGA project
6.4 The example synthesis code
6.5 Modifications on the C/C++ code for synthesis
6.6 simple.c: An example of a host program
6.7 practical.c: A practical host program
6.8 Design considerations
6.8.1 Working with multiple AXI streams
6.8.2 The application clock’s frequency
6.8.3 Resetting the logic
