wire fifo_pre_rd_en; wire fifo_pre_empty; wire [511:0] fifo_pre_dout; wire [9:0] fifo_pre_rd_count; wire fifo_post_wr_en; wire fifo_post_full; wire [511:0] fifo_post_din; wire [9:0] fifo_post_wr_count; wire axi_clk; wire axi_aresetn; wire [31:0] axi_awaddr; wire [7:0] axi_awlen; wire [2:0] axi_awsize; wire [1:0] axi_awburst; wire axi_awvalid; wire axi_awready; wire [511:0] axi_wdata; wire [63:0] axi_wstrb; wire axi_wlast; wire axi_wvalid; wire axi_wready; wire axi_bvalid; wire axi_bready; wire [31:0] axi_araddr; wire [7:0] axi_arlen; wire [2:0] axi_arsize; wire [1:0] axi_arburst; wire axi_arvalid; wire axi_arready; wire [511:0] axi_rdata; wire axi_rlast; wire axi_rvalid; wire axi_rready; deepfifo #( .log2_ram_size_addr(30), .log2_word_width(9), .log2_fifo_words(9), .fifo_threshold(256) ) deepfifo_inst ( .clk (axi_clk), .reset (sys_rst), // Active high .fifo_pre_rd_en (fifo_pre_rd_en), .fifo_pre_empty (fifo_pre_empty), .fifo_pre_dout (fifo_pre_dout), .fifo_pre_rd_count (fifo_pre_rd_count), .fifo_post_wr_en (fifo_post_wr_en), .fifo_post_din (fifo_post_din), .fifo_post_full (fifo_post_full), .fifo_post_wr_count (fifo_post_wr_count), .axi_aresetn (axi_aresetn), .axi_awaddr (axi_awaddr), .axi_awlen (axi_awlen), .axi_awvalid (axi_awvalid), .axi_awready (axi_awready), .axi_awsize (axi_awsize), .axi_awburst (axi_awburst), .axi_wdata (axi_wdata), .axi_wstrb (axi_wstrb), .axi_wlast (axi_wlast), .axi_wvalid (axi_wvalid), .axi_bvalid (axi_bvalid), .axi_bready (axi_bready), .axi_araddr (axi_araddr), .axi_arlen (axi_arlen), .axi_arvalid (axi_arvalid), .axi_arready (axi_arready), .axi_arsize (axi_arsize), .axi_arburst (axi_arburst), .axi_wready (axi_wready), .axi_rdata (axi_rdata), .axi_rready (axi_rready), .axi_rlast (axi_rlast), .axi_rvalid (axi_rvalid) ); memctl memctl_inst ( // Memory interface ports .ddr3_addr (ddr3_addr), // output [13:0] ddr3_addr .ddr3_ba (ddr3_ba), // output [2:0] ddr3_ba .ddr3_cas_n (ddr3_cas_n), // output ddr3_cas_n .ddr3_ck_n (ddr3_ck_n), // output [0:0] ddr3_ck_n .ddr3_ck_p (ddr3_ck_p), // output [0:0] ddr3_ck_p .ddr3_cke (ddr3_cke), // output [0:0] ddr3_cke .ddr3_ras_n (ddr3_ras_n), // output ddr3_ras_n .ddr3_reset_n (ddr3_reset_n), // output ddr3_reset_n .ddr3_we_n (ddr3_we_n), // output ddr3_we_n .ddr3_dq (ddr3_dq), // inout [63:0] ddr3_dq .ddr3_dqs_n (ddr3_dqs_n), // inout [7:0] ddr3_dqs_n .ddr3_dqs_p (ddr3_dqs_p), // inout [7:0] ddr3_dqs_p .init_calib_complete (), // output init_calib_complete .ddr3_cs_n (ddr3_cs_n), // output [0:0] ddr3_cs_n .ddr3_dm (ddr3_dm), // output [7:0] ddr3_dm .ddr3_odt (ddr3_odt), // output [0:0] ddr3_odt // Application interface ports .ui_clk (axi_clk), // output ui_clk .ui_clk_sync_rst (), // output ui_clk_sync_rst .mmcm_locked (), // output mmcm_locked .aresetn (axi_aresetn), // input aresetn .app_sr_req (1'b0), // input app_sr_req .app_ref_req (1'b0), // input app_ref_req .app_zq_req (1'b0), // input app_zq_req .app_sr_active (), // output app_sr_active .app_ref_ack (), // output app_ref_ack .app_zq_ack (), // output app_zq_ack // Slave Interface Write Address Ports .s_axi_awid (4'd0), // input [3:0] s_axi_awid .s_axi_awaddr (axi_awaddr), // input [29:0] s_axi_awaddr .s_axi_awlen (axi_awlen), // input [7:0] s_axi_awlen .s_axi_awsize (axi_awsize), // input [2:0] s_axi_awsize .s_axi_awburst (axi_awburst), // input [1:0] s_axi_awburst .s_axi_awlock (1'b0), // input [0:0] s_axi_awlock .s_axi_awcache (4'd0), // input [3:0] s_axi_awcache .s_axi_awprot (3'd0), // input [2:0] s_axi_awprot .s_axi_awqos (4'd0), // input [3:0] s_axi_awqos .s_axi_awvalid (axi_awvalid), // input s_axi_awvalid .s_axi_awready (axi_awready), // output s_axi_awready // Slave Interface Write Data Ports .s_axi_wdata (axi_wdata), // input [511:0] s_axi_wdata .s_axi_wstrb (axi_wstrb), // input [63:0] s_axi_wstrb .s_axi_wlast (axi_wlast), // input s_axi_wlast .s_axi_wvalid (axi_wvalid), // input s_axi_wvalid .s_axi_wready (axi_wready), // output s_axi_wready // Slave Interface Write Response Ports .s_axi_bid (), // output [3:0] s_axi_bid .s_axi_bresp (), // output [1:0] s_axi_bresp .s_axi_bvalid (axi_bvalid), // output s_axi_bvalid .s_axi_bready (axi_bready), // input s_axi_bready // Slave Interface Read Address Ports .s_axi_arid (4'd0), // input [3:0] s_axi_arid .s_axi_araddr (axi_araddr), // input [29:0] s_axi_araddr .s_axi_arlen (axi_arlen), // input [7:0] s_axi_arlen .s_axi_arsize (axi_arsize), // input [2:0] s_axi_arsize .s_axi_arburst (axi_arburst), // input [1:0] s_axi_arburst .s_axi_arlock (1'b0), // input [0:0] s_axi_arlock .s_axi_arcache (4'd0), // input [3:0] s_axi_arcache .s_axi_arprot (3'd0), // input [2:0] s_axi_arprot .s_axi_arqos (4'd0), // input [3:0] s_axi_arqos .s_axi_arvalid (axi_arvalid), // input s_axi_arvalid .s_axi_arready (axi_arready), // output s_axi_arready // Slave Interface Read Data Ports .s_axi_rid (), // output [3:0] s_axi_rid .s_axi_rdata (axi_rdata), // output [511:0] s_axi_rdata .s_axi_rresp (), // output [1:0] s_axi_rresp .s_axi_rlast (axi_rlast), // output s_axi_rlast .s_axi_rvalid (axi_rvalid), // output s_axi_rvalid .s_axi_rready (axi_rready), // input s_axi_rready // System Clock Ports .sys_clk_p (sys_clk_p), // input sys_clk_p .sys_clk_n (sys_clk_n), // input sys_clk_n .sys_rst (!sys_rst) // Active low ); fifo_512 fifo_pre ( .wr_clk(user_clk), .rd_clk(axi_clk), .rst(sys_rst), .din(), .wr_en(), .rd_en(fifo_pre_rd_en), .dout(fifo_pre_dout), .full(), .rd_data_count(fifo_pre_rd_count), .wr_data_count(), .empty(fifo_pre_empty) ); fifo_512 fifo_post ( .wr_clk(axi_clk), .rd_clk(user_clk), .rst(sys_rst), .din(fifo_post_din), .wr_en(fifo_post_wr_en), .rd_en(), .dout(), .full(fifo_post_full), .rd_data_count(), .wr_data_count(fifo_post_wr_count), .empty() );